As shown in FIG. 1, a typical computer system 10 has, among other components, a microprocessor 12, one or more forms of memory 14, integrated circuits 16 having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths 18, e.g., wires, buses, etc., to accomplish the various tasks of the computer system 10.
Communication between computer system components (e.g., from microprocessor 12 in FIG. 1 to integrated circuit 16 in FIG. 1) occurs across input/output (I/O) interfaces designed to facilitate the flow of data between computer system components. In one type of I/O interface, both a clock signal and data on a data signal are transmitted from a transmitting circuit to a receiving circuit. The receiving circuit uses the clock signal to latch the incoming data.
Such I/O interfaces in which a clock signal of a transmitting circuit is propagated to a receiving circuit for recovering data sent to the receiving circuit are referred to in the art as “source-synchronous” I/O interfaces. FIG. 2 shows an example of a source-synchronous I/O interface 20. Particularly, FIG. 2 shows an interface between a microprocessor 22 and an application specific integrated circuit (ASIC) 24. The microprocessor 22 transmits a data signal, DATA 26, and a clock signal, CLK 28, to the ASIC 24. The ASIC 24 uses the clock signal 28 to latch the incoming data on the data signal 26. Further, data on a data signal 30 and a clock signal 31 may be transmitted from the ASIC 24 to the microprocessor 22.
FIG. 3 shows another example of a source-synchronous I/O interface 40. Particularly, FIG. 3 shows an interface between a microprocessor 42 and a memory circuit 44. The microprocessor 42 transmits a data signal, DATA 48, and a clock signal, CLK 50 to the memory circuit 44. The memory circuit 44 uses the clock signal 50 to latch incoming data on the data signal 48.
In addition to the data signal 48 and the clock signal 50, the microprocessor 42 may transmit an index signal, INDEX 46. The index signal 46 is used to index one or more particular address locations in the memory circuit 44. Further, data on a data signal 52 and a clock signal 53 may be transmitted from the memory circuit 44 to the microprocessor 42.
With respect to a typical I/O interface, such as the ones shown in FIGS. 2 and 3, data is transmitted in a series of binary 0's and 1's from a transmitting circuit (e.g., microprocessor 42 in FIG. 3) to a receiving circuit (e.g., memory circuit 44 in FIG. 3). Accordingly, at any particular time, a data signal received at the receiving circuit may have a low voltage potential representative of a binary “0” or a high voltage potential representative of a binary “1.” In order to properly latch such incoming data at a rate equal to the rate at which the data is being sent, a clock signal (e.g., 50 in FIG. 3) sent with the data from the transmitting circuit is used to latch and recover the data at the receiving circuit. Thus, the receiving circuit has a proper reference of time to latch incoming data. Moreover, such an arrangement helps gain timing margins that were lost due to uncertainties of integrated circuit topologies.
In order to drive a clock signal and data on a data signal across an I/O interface, a transmitting circuit uses driver circuitry (“drivers”). As will be further discussed below with reference to FIG. 4, one or more drivers drive data (i.e., data drivers) and one or more drivers drive the clock signal (i.e., clock drivers). For ideal performance, the delays of the path along which the data driver(s) resides and the path along which the clock driver(s) resides should be equal in order to minimize resulting skew between the data and the clock signal at the receiving circuit. However, due to various variations such as power variations, temperature variations, process variations, package trace variations, etc., the delays of the I/O data path (i.e., the path along which the data driver(s) resides) and the I/O clock path (i.e., the path along which the clock driver(s) resides) are often unequal (i.e., mismatched). Such mismatched delays results in the misalignment of the data and the clock signal, which, in turn, may cause inaccurate data capture at the receiving circuit.
In addition to mismatched delays of the driver and clock paths, the speed of communication, or data transmission, across an I/O interface is not commensurate with the increase of integrated circuit and microprocessor speeds. In other words, I/O interface speeds are not increasing at the same rate as processor speeds. Because of this, I/O interface speeds often serve as a bottleneck (i.e., a limiting factor) with respect to overall speed performance in a computer system.